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STM6502, STM6503 STM6504, STM6505
Dual push-button Smart ResetTM with user-adjustable setup delays
Features

Dual Smart Reset push-button inputs with extended reset setup delay Adjustable Smart Reset setup delay (tSRC): by external capacitor or three-state logic (product options): tSRC = 2, 6, 10 s (min.) Power-on reset Single RST output, active-low, open-drain Factory-programmable thresholds to monitor VCC in the range of 1.575 to 4.625 V typ. Operating voltage 1.0 V (active-low output valid) to 5.5 V Low supply current Operating temperature: industrial grade -40 C to +85 C TDFN8 package: 2 mm x 2 mm x 0.75 mm RoHS compliant
TDFN8 (DG) 2 mm x 2 mm

Applications

Mobile phones, smartphones e-books MP3 players Games Portable navigation devices Any application that requires delayed reset push-button(s) response for improved system stability

Table 1.
Device summary
Voltage inputs Smart Reset inputs tSRC programming Threestate input TSR RST BLD Reset or Power Good outputs
Part number VCC VBAT SR0 SR1
SRE Ext. immediate, SRC pin independent
Package
STM6502(1) STM6503 STM6504(1) STM6505

TDFN-8L TDFN-8L TDFN-8L TDFN-8L
1. Contact local ST sales office for availability.
June 2010
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www.st.com 1
Contents
STM6502, STM6503, STM6504, STM6505
Contents
1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.1 1.2 Smart Reset devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.2.1 1.2.2 1.2.3 1.2.4 1.2.5 1.2.6 1.2.7 1.2.8 1.2.9 1.2.10 Power supply (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Ground (VSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Primary Smart Reset input (SR0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Secondary Smart Reset input (SR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Edge-triggered Smart Reset input (SRE pin) - STM6504 only . . . . . . . 11 Adjustable delay of Smart Reset input (SRC pin) - STM6502 and STM6505 only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Programmable Smart Reset input delay (TSR pin) - STM6503 and STM6504 only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Reset output (RST) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Battery monitoring input (VBAT) - STM6505 only . . . . . . . . . . . . . . . . . 12 Battery low detect output (BLD) - STM6505 only . . . . . . . . . . . . . . . . . 12
2 3 4 5 6 7 8
Typical operating characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Package marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
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List of tables
List of tables
Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 tSRC programmed by an ideal external capacitor - STM6502 and STM6505 . . . . . . . . . . 11 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Operating and measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 DC and AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 VCC voltage thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 TDFN - 8-lead 2 x 2 x 0.75 mm, 0.5 mm pitch package mechanical data . . . . . . . . . . . . . 21 Parameter for landing pattern - TDFN - 8-lead 2 x 2 mm package . . . . . . . . . . . . . . . . . . 22 Carrier tape dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Reel dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Package marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
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STM6502, STM6503, STM6504, STM6505
List of figures
List of figures
Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Logic diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Block diagram - STM6502, STM6503, STM6504 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Block diagram - STM6505 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Single-button Smart Reset typical hookup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Dual-button Smart Reset typical hookup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 STM6502, STM6503 timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 STM6504 timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 STM6505 timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Supply current (ICC) vs. temperature (STM6505) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Smart Reset delay (tSRC) vs. temperature, CSRC = 0.62 F (STM6505) . . . . . . . . . . . . . . 13 Reset threshold (VRST) vs. temperature, "S" threshold option, VCC falling (STM6505) . . . 14 VBAT monitoring threshold (VBATTH) vs. temperature, falling (STM6505) . . . . . . . . . . . . . . 14 AC testing input/output waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 TDFN - 8-lead 2 x 2 x 0.75 mm, 0.5 mm pitch package outline . . . . . . . . . . . . . . . . . . . . . 21 Landing pattern - TDFN - 8-lead 2 x 2 mm without thermal pad . . . . . . . . . . . . . . . . . . . . 22 Carrier tape . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Reel dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Tape trailer/leader. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Pin 1 orientation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Package marking, top view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
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STM6502, STM6503, STM6504, STM6505
Description
1
Description
STM6502 has two combined Smart Reset inputs (SR0 and SR1) with delayed Smart Reset setup time (tSRC) programmed by an external capacitor on the SRC pin. STM6503 is similar to STM6502, has two combined delayed Smart Reset inputs (SR0, SR1) and three user-selectable delayed Smart Reset setup time (tSRC) options of 2 s, 6 s and 10 s through a three-state TSR input pin: when connected to ground, tSRC = 2 s; when left open, tSRC = 6 s; when connected to VCC, tSRC = 10 s (all the times are minimum). STM6504 has two independent Smart Reset inputs. SR0 provides the delayed Smart Reset setup time (tSRC) function with three user-selectable tSRC options through a three-state TSR input pin: when connected to ground, tSRC = 2 s; when left open, tSRC = 6 s; when connected to VCC, tSRC = 10 s (all the times are minimum). SRE provides instant reset. SRE is edge-triggered with a special debounce time (tDEBOUNCE = 240 ms min.) at the falling edge after a valid reset period. STM6505 has two combined delayed Smart Reset inputs (SR0, SR1) and provides an adjustable reset delay setup time via an external capacitor connected to the SRC pin. The RST output depends also on the VCC monitoring threshold. STM6505 also provides independent low battery detect (BLD) output controlled by the secondary external input voltage VBAT. VBAT is monitored for low voltage and provides an indication on the battery low detect output pin (BLD). VBAT threshold is 1.25 V, fixed, and an external resistor divider is to be used to set the actual battery voltage threshold. VBAT threshold hysteresis is 8 mV typ. (16 mV max.). VBAT is voltage monitoring input only, the device is powered only from the VCC pin; VCC must be 1.575 V for proper operation of the VBAT comparator.
1.1
Smart Reset devices
The Smart Reset device family STM65xx provides a useful feature that ensures inadvertent short reset push-button closures do not cause system resets. This is done by implementing extended Smart Reset input delay (tSRC). Once the valid Smart Reset input levels and setup delay are met, the device generates an output reset pulse with user-programmable timeout period (tREC). The Smart Reset inputs can be also connected to the applications interrupt to allow the control of both the interrupt pin and the hard reset functions. If the push-buttons are closed for a short time, the processor is only interrupted. If the system still does not respond properly, holding the push-buttons for the extended setup time (tSRC) causes hard reset of the processor through the reset outputs. The Smart Reset feature helps significantly increase system stability. The STM65xx family of Smart Reset devices consists of low current microprocessor reset circuits targeted at applications such as MP3 players, navigation, smartphones or mobile phones; generally any application that requires delayed reset push-button(s) response for improved system stability. The STM65xx devices feature single or dual Smart Reset inputs (SR). The delayed Smart Reset setup time (tSRC) options of 2 s, 6 s and 10 s (all min.) are adjustable by an external capacitor on the SRC pin or selectable by three-state logic. The delayed setup period ignores switch closures shorter than tSRC, thus preventing unwanted resets.
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Description
STM6502, STM6503, STM6504, STM6505 The STM65xx devices have active-low (optionally active-high) open-drain reset (RST) output(s) with or without internal pull-up resistor or push-pull as output options, with factoryprogrammed or capacitor-adjustable or push-buttons defined output reset pulse duration, with or without power-on reset function. Some devices also have an undervoltage monitoring feature: the reset output is also asserted when the monitored supply voltage VCC drops below the specified threshold. The reset output remains asserted for the reset timeout period (tREC) after the monitored supply voltage goes above the specified threshold. Figure 1. Logic diagrams
VCC VCC
SR0 SR1 SRC
SR0
STM6502
RST
SR1 TSR
STM6503
RST
VSS
VSS
VCC
VCC
SR0 SRE TSR
SR0
STM6504
RST
SR1 SRC VBAT
RST
STM6505
BLD
VSS
VSS
AM00378
Figure 2.
Pin connections
RST VSS SR1 NC 1 2 3 4 8 VCC SR0 SRC NC RST VSS SR1 NC 1 2 3 4 8 VCC SR0 TSR NC
STM 6502
7 6 5
STM 6503
7 6 5
RST VSS SRE NC
1 2 3 4
8
VCC SR0 TSR NC
RST VSS SR1 BLD
1 2 3 4
8
VCC SR0 SRC VBAT
AM00379
STM 6504
7 6 5
STM 6505
7 6 5
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STM6502, STM6503, STM6504, STM6505 Table 2.
Symbol RST BLD SR0
Description
Signal names
Input/ output Output Output Input Description Open-drain reset output, active-low. Battery low detect output, active-low, open-drain. STM6505 only. Primary push-button Smart Reset input. Active-low, with or without internal 65 k pull-up to VCC (product options). Secondary push-button Smart Reset input - combines with the primary pushbutton reset to provide setup delay time before reset. Active-low, with or without internal 65 k pull-up to VCC (product options). Secondary push-button Smart Reset input - provides instant Smart Reset. SRE is edge-triggered with a special debounce time (tDEBOUNCE = 240 ms min.) at the falling edge after a valid reset period. Active-high, no internal pull-up to VCC. STM6504 only. Smart Reset input delay setup control: connect to an external capacitor to adjust the delay setup time (tSRC). STM6502 and STM6505 only. A three-state Smart Reset input delay setup control. When connected to ground, tSRC = 2 s; when left open, tSRC = 6 s; when connected to VCC, tSRC = 10 s (all times are minimum). TSR is a DC-type input, intended to be either permanently grounded, permanently connected to VCC or permanently left open. If left open, for improved system glitch immunity it is strongly recommended to connect a 0.1 F decoupling ceramic capacitor between the TSR and VSS pins. STM6503 and STM6504 only. Supply voltage input. Power supply for the device and an input for the monitored supply voltage. A 0.1 F decoupling ceramic capacitor is recommended to be connected between the VCC and VSS pins. Battery voltage monitoring input. STM6505 only. Ground No connect (not bonded); should be connected to VSS.
SR1
Input
SRE
Input
SRC
Input
TSR
Input
VCC VBAT VSS NC
Supply Input Supply
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Description Figure 3.
STM6502, STM6503, STM6504, STM6505 Block diagram - STM6502, STM6503, STM6504
VCC VRST COMPARE
SR1 (SRE STM6504 only)(1)
Logic tREC generator Logic RST
SR0 SRC (STM6502) TSR (STM6503, STM6504)
AM00352a
1. STM6504 only: SR0 and SRE are working independently. SRE is edge-triggered and has a special debounce time (tDEBOUNCE = 240 ms min.) at the falling edge after a valid reset period.
Figure 4.
Block diagram - STM6505
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STM6502, STM6503, STM6504, STM6505 Figure 5. Single-button Smart Reset typical hookup
Description
Figure 6.
Dual-button Smart Reset typical hookup
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Description
STM6502, STM6503, STM6504, STM6505
1.2
1.2.1
Pin descriptions
Power supply (VCC)
This pin is used to provide the power to the device and to monitor the power supply. A 0.1 F decoupling ceramic capacitor is recommended to be connected between the VCC and VSS pins.
1.2.2
Ground (VSS)
This is the supply ground for the device.
1.2.3
Primary Smart Reset input (SR0)
The primary push-button Smart Reset input, active-low pin is connected to the first pushbutton switch.
1.2.4
Secondary Smart Reset input (SR1)
The secondary push-button Smart Reset input, active-low pin is connected to the second push-button switch. Keeping both Smart Reset inputs SR0 and SR1 active for longer than tSRC activates the reset output pulse. Figure 7. STM6502, STM6503 timing
tSRC SR0 tREC
SR1
RST
AM00327
Reset is asserted "low" right after the Smart Reset setup delay (tSRC) has been met and returns to high after the tREC period.
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Description
1.2.5
Edge-triggered Smart Reset input (SRE pin) - STM6504 only
The SRE pin is active-high, immediate and independent reset input that includes an edge trigger with debounce delay tDEBOUNCE on the falling edge.
Note:
The triggering edge must be a high-to-low or low-to-high transition with a slew-rate faster than 1 V/s typ. Figure 8. STM6504 timing
t < tDEBOUNCE => tREC timer reset SR0 Independent SRE RST No debounce tREC tDEBOUNCE tREC (rising edges within tDEBOUNCE are ignored) tREC t < tSRC => no output response tSRC
AM00328V2
1.2.6
Adjustable delay of Smart Reset input (SRC pin) - STM6502 and STM6505 only
This pin controls the setup time before the push-button action is validated by the reset output. It is connected to an external capacitor (CSRC), which is tied to ground to provide the desired value of the setup time (tSRC). Calculated tSRC and CSRC examples are given in Table 3. Refer also to Table 6. Table 3. tSRC programmed by an ideal external capacitor - STM6502 and STM6505
Setup delay tSRC [s](1)(2) Min. 2 3 6 10 Typ. 2.5 3.75 7.5 12.5 Max. 3.0 4.5 9 15 Closest common CSRC value [F] 0.22 0.33 0.56 1
Calculated CSRC value [F] 0.2 0.3 0.6 1
1. At 25 C. Example calculations based on an ideal capacitor. During application design and component selection it should be considered that the current flowing into the external tSRC programming capacitor (CSRC) is on the order of 100 nA, therefore a low-leakage capacitor (ceramic or film capacitor) should be used and placed as close as possible to the SRC pin. Also an adequate low-leakage PCB environment should be ensured to prevent tSRC accuracy from being affected. A recommended minimum value of CSRC is 0.01 F. 2. In case of repeated activations of the tSRC timer, an interval of 10 ms min. is needed between the activations to fully discharge C SRC, so that the next tSRC is as specified.
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Description
STM6502, STM6503, STM6504, STM6505
1.2.7
Programmable Smart Reset input delay (TSR pin) - STM6503 and STM6504 only
The TSR pin allows the user to program the setup time before the push-button action is validated by the reset output. It is controlled by different voltage levels on the three-state TSR input pin: when connected to ground, tSRC = 2 s; when left open, tSRC = 6 s; when connected to VCC, tSRC = 10 s (all times are minimum). TSR is a DC-type input, intended to be either permanently grounded, permanently connected to VCC or permanently left open. If it is left open, for improved system glitch immunity it is strongly recommended to connect a 0.1 F decoupling ceramic capacitor between the TSR and VSS pins.
1.2.8
Reset output (RST)
RST is the active-low, open-drain reset output in the Smart Reset family.
1.2.9
Battery monitoring input (VBAT) - STM6505 only
VBAT is an input for monitoring the battery voltage. VBAT threshold is 1.25 V, fixed, and an external resistor divider is to be used to set the actual battery voltage threshold.
1.2.10
Battery low detect output (BLD) - STM6505 only
The battery low detect output is controlled by the VBAT voltage monitoring input and is active-low, open-drain, with no pull-up. Figure 9. STM6505 timing
tSRC SR0 tREC
SR1
RST VBAT VBATTH BLD
AM00329
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Typical operating characteristics
2
Typical operating characteristics
Figure 10. Supply current (ICC) vs. temperature (STM6505)
3
2.5
2
ICC [A]
1.5
1
0.5
0 -60 -40 -20 0 20 40 Temperature [C] 5.5 V 2V 5V 3V
AM04886v1
60
80
100
120
140
Figure 11. Smart Reset delay (tSRC) vs. temperature, CSRC = 0.62 F (STM6505)
9.2
8.7
8.2
tSRC [s]
7.7
7.2
6.7
6.2 -60 -40 -20 0 20 40 Temperature [C] 5.75 V 5.5 V 3.3 V
AM04887v1
60
80
100
120
140
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Typical operating characteristics
STM6502, STM6503, STM6504, STM6505
Figure 12. Reset threshold (VRST) vs. temperature, "S" threshold option, VCC falling (STM6505)
2.99
2.97
2.95
VRST [V]
2.93
2.91
2.89
2.87
2.85 -60 -40 -20 0 20 40 Temperature [C]
AM04888v1
60
80
100
120
140
Figure 13. VBAT monitoring threshold (VBATTH) vs. temperature, falling (STM6505)
1.275 1.27 1.265 1.26
VBATTH [V]
1.255 1.25 1.245 1.24 1.235 1.23 1.225 -60 -40 -20 0 20 40 Temperature [C] 5.75 V 5.5 V 3.3 V 2V 1.58 V
AM04889v1
60
80
100
120
140
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Maximum ratings
3
Maximum ratings
Stressing the device above the rating listed in Table 4: Absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. Table 4.
Symbol TSTG TSLD(1)
Absolute maximum ratings
Parameter Storage temperature (VCC off) Lead solder temperature for 10 seconds Thermal resistance (junction to ambient) Input or output voltage Supply voltage TDFN8 Value -55 to +150 260 149.0 -0.3 to 5.5(2) -0.3 to 7 Unit C C C/W V V
JA
VIO VCC
1. Reflow at peak temperature of 260 C. The time above 255 C must not exceed 30 seconds. 2. For inputs or outputs with internal pull-up resistors and push-pull type outputs -0.3 to VCC +0.3 V only.
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DC and AC parameters
STM6502, STM6503, STM6504, STM6505
4
DC and AC parameters
This section summarizes the operating measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC characteristics tables that follow, are derived from tests performed under the measurement conditions summarized in Table 5: Operating and measurement conditions. Designers should check that the operating conditions in their circuit match the operating conditions when relying on the quoted parameters. Table 5. Operating and measurement conditions
Parameter VCC supply voltage Ambient operating temperature (TA) Input rise and fall times Input pulse voltages Input and output timing ref. voltages Value 1.0 to 5.5 -40 to +85 5 0.2 to 0.8 V CC 0.3 to 0.7 V CC Unit V C ns V V
Figure 14. AC testing input/output waveforms
0.8 VCC 0.2 VCC 0.7 VCC 0.3 VCC
AM00478
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STM6502, STM6503, STM6504, STM6505 Table 6.
Symbol VCC
DC and AC parameters
DC and AC characteristics
Parameter Supply voltage range Test conditions(1) Reset output valid - active-low STM6502 VCC = 5.0 V VCC = 3.0 V STM6503
(3)
Min. 1.0
Typ.(2)
Max. 5.5
Unit V A A
1.2 1.1 4
(3)
VCC = 5.0 V, TSR left open VCC = 3.0 V, TSR left open
5.8
A A
ICC
Supply current (inputs in their inactive state) STM6504
3 4 5.8
VCC = 5.0 V, TSR left open VCC = 3.0 V, TSR left open
(3)
A A
3 2.3 2.2 3.3
STM6505 Output characteristics
VCC = 5.0 V VCC = 3.0 V(3)
A A
VCC 4.5 V, sinking 3.2 mA VOL Reset output voltage low (reset asserted: RST, BLD) VCC 3.3 V, sinking 2.5 mA VCC 1.0 V, sinking 0.1 mA tREC Reset timeout delay, factory-programmed Option A Option B 140 240 210 360
0.3 0.3 0.3 280 480
V V V ms ms
VCC monitoring reset thresholds Fixed voltage trip point for VCC monitoring (refer to Table 7) -40 to +85 C 25 C L, M VHYST Hysteresis of VRST T, S, R, Z, Y, W, V VCC falling from (VRST + 100 mV) to (VRST - 100 mV) at 10 mV/s(4) VRST -2.5% VRST -2.0% VRST VRST 0.5% 1% 20 s VRST +2.5% VRST +2.0% V V
VRST
VCC to reset delay VBAT monitoring VBATTH VBATHYST ILI(VBAT) Fixed VBAT monitoring threshold VBATTH hysteresis VBAT input leakage current
STM6505 only STM6505 only STM6505 only
1.225
1.25 8
1.275 16 100
V mV nA
-100
10
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DC and AC parameters Table 6.
Symbol Smart Reset inputs VIL VIH ILI(SR) ILI(TSR) SR0, SR1, SRE input voltage low SR0, SR1, SRE input voltage high Input leakage current, SR and SRE inputs Input leakage current, TSR input Internal pull-up resistor, input (optional - refer to Table 12) SRE input falling edge debounce time STM6504 only
STM6502, STM6503, STM6504, STM6505
DC and AC characteristics (continued)
Parameter Test conditions(1) Min. Typ.(2) Max. Unit
VSS -0.3 0.7 VCC Option without internal pull-up resistor STM6503 and STM6504 only -1 -5
0.3 VCC 5.5 +1 +7
V V A A
RPUI
65
k
tDEBOUNCE
240
360
480
ms
Smart Reset delay Capacitor-programmable Smart Reset setup time, STM6502 and STM6505. Refer to Table 3. TSR pin-programmable Smart Reset setup time, STM6503 and STM6504. 10 x CSRC (F) 2 6 10 12.5 x CSRC (F) 2.5 7.5 12.5 15 x CSRC (F) 3 9 15
tSRC
(5)
TA = 25 C
s
TSR = VSS TSR = floating(6)
s s s
tSRC
(5)
TSR = VCC
1. Valid for ambient operating temperature: TA = -40 to +85 C; VCC = 1.0 to 5.5 V (except where noted). 2. Typical value is at 25 C and VCC = 3.3 V unless otherwise noted. 3. For devices with VRST < 3.0 V. 4. Guaranteed by design. 5. Input glitch immunity is equal to tSRC (when both SR inputs are low, otherwise infinite). STM6502, STM6503, STM6505 only. 6. If left open, for improved system glitch immunity it is strongly recommended to connect a 0.1 F decoupling ceramic capacitor between the TSR and VSS pins.
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Doc ID 16101 Rev 5
STM6502, STM6503, STM6504, STM6505 Table 7.
.
DC and AC parameters
VCC voltage thresholds
2.5% (-40 C to +85 C) Typ. Min. 4.625 4.375 3.075 2.925 2.625 2.313 2.188 1.665 1.575 4.509 4.266 2.998 2.852 2.559 2.255 2.133 1.623 1.536 Max. 4.741 4.484 3.152 2.998 2.691 2.371 2.243 1.707 1.614 Min. 4.533 4.288 3.014 2.867 2.573 2.267 2.144 1.632 1.544 Max. 4.718 4.463 3.137 2.984 2.678 2.359 2.232 1.698 1.607 V V V V V V V V V 2.0% (25 C) Unit
VCC monitoring threshold VRST L (falling) M (falling) T (falling) S (falling) R (falling) Z (falling) Y (falling) W (falling) V (falling)
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Package mechanical data
STM6502, STM6503, STM6504, STM6505
5
Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK(R) packages, depending on their level of environmental compliance. ECOPACK(R) specifications, grade definitions and product status are available at: www.st.com. ECOPACK(R) is an ST trademark.
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STM6502, STM6503, STM6504, STM6505
Package mechanical data
Figure 15. TDFN - 8-lead 2 x 2 x 0.75 mm, 0.5 mm pitch package outline
D A B
PIN 1 INDEX AREA
E
0.10 C 2x
0.10 C 2x TOP VIEW 0.10 C
A
A1
SEAT ING PLANE SIDE VIEW
C
0.08 C e
PIN 1 INDEX AREA
b
1 4
0.10
CAB
Pin#1 ID
L
8
BOTTOM VIEW
5
8070540_A
Table 8.
Symbol
TDFN - 8-lead 2 x 2 x 0.75 mm, 0.5 mm pitch package mechanical data
Dimension (mm) Min. Nom. 0.75 0.02 0.20 2.00 2.00 0.50 0.45 0.55 0.65 0.018 Max. 0.80 0.05 0.25 2.1 2.1 Min. 0.028 0.000 0.006 0.075 0.075 Dimension (inches) Nom. 0.030 0.001 0.008 0.079 0.079 0.020 0.022 0.026 Max. 0.031 0.002 0.010 0.083 0.083
A A1 b D BSC E BSC e L
0.70 0.00 0.15 1.9 1.9
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Package mechanical data
STM6502, STM6503, STM6504, STM6505
Figure 16. Landing pattern - TDFN - 8-lead 2 x 2 mm without thermal pad
D P
E
E1
L
b
AM00441
Table 9.
Parameter L b E E1 D P
Parameter for landing pattern - TDFN - 8-lead 2 x 2 mm package
Dimension (mm) Description Min. Contact length Contact width Max. land pattern Y-direction Contact gap spacing Max. land pattern X-direction Contact pitch 1.05 0.25 Nom. Max. 1.15 0.30
-- --
2.85 0.65 1.75 0.5
-- -- -- --
-- -- -- --
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Doc ID 16101 Rev 5
STM6502, STM6503, STM6504, STM6505 Figure 17. Carrier tape
P0 D T A0 Top cover tape B0 P2
Package mechanical data
E
F W
K0
Center lines of cavity User direction of feed
P1
AM03073v2
Table 10.
Package
Carrier tape dimensions
W 8.00 +0.30 -0.10 D 1.50 +0.10/ -0.00 E P0 P2 F A0 2.30 0.05 B0 2.30 0.05 K0 1.00 0.05 P1 4.00 0.10 T 0.250 0.05 Unit Bulk qty.
TDFN8
1.75 4.00 2.00 3.50 0.10 0.10 0.10 0.05
mm 3000
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Package mechanical data Figure 18. Reel dimensions
STM6502, STM6503, STM6504, STM6505
T
40 mm min. acces hole at slot location B
D A
C
N
Full radius Tape slot in core for tape start 25 mm min width G measured at hub
AM00443
Table 11.
Tape sizes 8 mm
Reel dimensions
A max. 180 (7 inches) B min. 1.50 C 13.0 +/- 0.20 D min. 20.20 N min. 60 G 8.4 +2/-0 T max. 14.40
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Doc ID 16101 Rev 5
STM6502, STM6503, STM6504, STM6505 Figure 19. Tape trailer/leader
End
Package mechanical data
Start
Top cover tape
No components T RA IL ER 160 mm min.
Components
100 mm min.
No components L EA D ER
400 mm min.
Sealed with cover tape
User direction of feed
AM00444
Figure 20. Pin 1 orientation
User direction of feed
AM00442
Note:
1 2
Drawings are not to scale. All dimensions are in mm, unless otherwise noted.
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Part numbering
STM6502, STM6503, STM6504, STM6505
6
Table 12.
Example: Device type STM6502(1) STM6503 STM6504(1) STM6505
Part numbering
Ordering information scheme
STM6505 W C A B DG 6 F
Reset (VCC monitoring) threshold voltage (VRST), typ., falling L = 4.625 V S = 2.925 V R = 2.625 V Z = 2.313 V W = 1.665 V V = 1.575 V Smart Reset setup delay (tSRC); presence of internal input pull-up on all Smart Reset inputs (SRx, SRE) A = user-programmable (external capacitor); no input pull-up C = user-programmable (external capacitor); 65 k input pull-up E = 2 or 6 or 10 s min., user-programmable (three-state); no input pull-up F = 2 or 6 or 10 s min., user-programmable (three-state); 65 k input pull-up Output type A = open-drain, no pull-up, active-low Reset timeout period (tREC) A = 140 ms min. B = 240 ms min. Package DG = TDFN8 2 x 2 x 0.75 mm, 0.5 mm pitch Temperature range 6 = -40 C to +85 C Shipping method F = ECOPACK(R) package, tape and reel 1. Contact local ST sales office for availability.
For device options currently available refer to Table 13. For other options, voltage threshold values etc. or for more information on any aspect of this device, please contact the ST sales office nearest you.
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Doc ID 16101 Rev 5
STM6502, STM6503, STM6504, STM6505
Package marking
7
Package marking
Table 13. Package marking
tSRC delay control TSR TSR CSRC CSRC CSRC Smart Reset inputs(1) AL AL AL, PU AL, PU AL, PU VRST V S S R W RST output(1) AL, OD AL, OD AL, OD AL, OD AL, OD tREC BLD option output(1) A B B B B -- -- AL, OD AL, OD AL, OD Topmark 3VG 4SG 5SK 5RK 5WK
Part number STM6503VEAADG6F STM6504SEABDG6F
(2)
STM6505SCABDG6F STM6505RCABDG6F STM6505WCABDG6F
1. AL = active-low, AH = active-high, PU = with internal pull-up resistor, OD = open-drain. 2. Contact local ST sales office for availability.
Figure 21. Package marking, top view
A
B
C
D
E
Topmark
A = dot (pin 1 reference) B = assembly plant (P) C = assembly year (Y, 0-9): 9 = 2009 etc. D = assembly work week (WW, 01 to 52): 20 = WW20 etc. E = marking area (topmark)
AM00479
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Revision history
STM6502, STM6503, STM6504, STM6505
8
Revision history
Table 14.
Date 31-Aug-2009
Document revision history
Revision 1 Initial release. Updated Applications, Section 1, Section , Figure 3 to Figure 6 updated and moved to Section , updated Table 1, Table 2, Table 3, Table 4, Table 6, Table 12, Section 1.2.3, Section 1.2.7, Section 1.2.9, Section 5, added package footprint, tape and reel information, and Section 7. Updated Features, Section 1, Section 1.2.6, Table 1, Table 2, Figure 5, Figure 6, Table 3, Table 6, Table 12, Table 13, removed Table 4. Updated title of datasheet, Features, Applications, Table 1, 2, 6, 12, footnote 5 of Table 6; updated Figure 3, 4; added Section 2: Typical operating characteristics; minor textual and formatting changes. Updated Features, Section 1, Figure 8, footnote 1 and 2 of Table 3, updated Table 4, added footnote 2 to Table 4, Table 6, added footnote 6 to Table 6, updated Table 6 to Table 9, and added footnote 2 of Table 13. Changes
06-Nov-2009
2
15-Jan-2010
3
01-Mar-2010
4
21-Jun-2010
5
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STM6502, STM6503, STM6504, STM6505
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